• Article  

      Adaptive packet scheduling over a wireless channel under constrained jamming 

      Fernández Anta, Antonio; Georgiou, Chryssis; Kowalski, D. R.; Zavou, Elli (2017)
      In this work we consider the communication over a wireless link, between a sender and a receiver, being disrupted by a jammer. The objective of the sender is to transmit as much data as possible to the receiver in the most ...
    • Article  

      Adaptive scheduling over a wireless channel under constrained jamming 

      Fernández Anta, Antonio; Georgiou, Chryssis; Zavou, Elli (2015)
      We consider a wireless channel between a single pair of stations (sender and receiver) that is being “watched” and disrupted by a malicious, adversarial jammer. The sender’s objective is to transmit as much useful data as ...
    • Article  

      Competitive analysis of task scheduling algorithms on a fault-prone machine and the impact of resource augmentation 

      Fernández Anta, Antonio; Georgiou, Chryssis; Kowalski, D. R.; Zavou, Elli (2015)
      Reliable task execution on machines that are prone to unpredictable crashes and restarts is both important and challenging, but not much work exists on the analysis of such systems. We consider the online version of the ...
    • Article  

      Computing Nash equilibria for scheduling on restricted parallel links 

      Gairing, M.; Lücking, T.; Mavronicolas, Marios; Monien, Burkhard (2010)
      We consider the problem of routing nusers on m parallel links under the restriction that each user may only be routed on a link from a certain set of allowed links for the user. So, this problem is equivalent to the ...
    • Conference Object  

      Hybrid CAC for MBMS-enabled 3G UMTS networks 

      Neophytou, Marios; Pitsillides, Andreas (2006)
      In this paper, a novel hybrid Connection Admission Control (CAC) scheme combining downlink transmission power and aggregate throughput in the case of dedicated and shared connection setup respectively, is presented ("DPTCAC: ...
    • Article  

      Measuring the impact of adversarial errors on packet scheduling strategies 

      Fernández Anta, A.; Georgiou, Chryssis; Kowalski, D. R.; Widmer, J.; Zavou, Elli (2016)
      In this paper, we explore the problem of achieving efficient packet transmission over unreliable links with worst-case occurrence of errors. In such a setup, even an omniscient offline scheduling strategy cannot achieve ...
    • Article  

      Online parallel scheduling of non-uniform tasks: Trading failures for energy 

      Fernández Anta, Antonio; Georgiou, Chryssis; Kowalski, D. R.; Zavou, Elli (2015)
      Consider a system in which tasks of different execution times arrive continuously and have to be executed by a set of machines that are prone to crashes and restarts. In this paper we model and study the impact of parallelism ...
    • Article  

      Online parallel scheduling of non-uniform tasks: Trading failures for energy 

      Fernández Anta, Antonio; Georgiou, Chryssis; Kowalski, D. R.; Zavou, Elli (2013)
      Consider a system in which tasks of different execution times arrive continuously and have to be executed by a set of processors that are prone to crashes and restarts. In this paper we model and study the impact of ...
    • Article  

      Packet scheduling over a wireless channel: AQT-based constrained jamming 

      Fernández Anta, Antonio; Georgiou, Chryssis; Zavou, Elli (2015)
      In this paper we consider a two-node setting with a sender transmitting packets to a receiver over a wireless channel. Unfortunately, the channel can be jammed, thus corrupting the packet that is being transmitted at the ...
    • Article  

      Rapid prototyping of the data-driven chip-multiprocessor (D 2-CMP) using FPGAs 

      Tatas, Konstantinos; Kyriacou, Costas; Evripidou, Paraskevas; Trancoso, Pedro; Wong, S. (2008)
      This paper presents the FPGA implementation of the prototype for the Data-Driven Chip-Multiprocessor (D2-CMP). In particular, we study the implementation of a Thread Synchronization Unit (TSU) on FPGA, a hardware unit that ...